1. Field
The present disclosure relates to verifying a layout of an integrated circuit (IC), and more particularly, to a method and system for verifying a layout of an IC including vertical memory cells.
2. Description of the Related Art
A designer may design an integrated circuit (IC) by preparing a schematic (or schematic data) of the IC so that the IC performs a desired function. The schematic of the IC may include various devices such as transistors, resistors, diodes, and the like, and define connectivity between the devices.
The designer may prepare layout data of the IC, which is implemented by stacking a plurality of layers on the basis of the schematic of the IC. The layout data of the IC may include topological data about the plurality of layers included in the IC, which is manufactured through semiconductor processes.